UPD750064CU datasheet(61/82 Pages) NEC

61 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

AC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle timeNote 1

tCY

Operates with

VDD = 2.7 to 5.5 V

0.67

µs

(minimum instruction

main system clock

0.95

µs

execution time = 1

Operates with

114

122

125

µs

machine cycle)

subsystem clock

TI0, TI1 input frequency

fTI

VDD = 2.7 to 5.5 V

1.0

MHz

275

kHz

TI0, TI1 input high-/low-level

tTIH, tTIL

VDD = 2.7 to 5.5 V

0.48

µs

width

1.8

µs

Interrupt input high-/

tINTH, tINTL

INT0

IM02 = 0

Note 2

µs

low-level width

IM02 = 1

µs

INT1, 2, 4

µs

KR0 to 3

µs

RESET low-level width

tRSL

µs

Notes 1.

The cycle time (minimum instruction

execution time) of the CPU clock (

Φ)

is determined by the oscillation frequency

of the connected resonator (and external

clock), the system clock control register

(SCC), and processor clock control

The figure on the right shows the supply

voltage VDD vs. cycle time tCY

characteristics when the device operates

with the main system clock.

2tCY or 128/fX depending on the setting

of the interrupt mode register (IM0).

0.5

(with main system clock)

tCY vs VDD

Guaranteed operation range

Supply voltage VDD [V]

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