UPD750064CU datasheet(57/82 Pages) NEC

57 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

XT1

XT2

Subsystem Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Resonator

Recommended

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Crystal

Oscillation frequency

32.768

kHz

resonator

(fXT)Note 1

Oscillation

VDD = 4.5 to 5.5 V

1.0

stabilization timeNote 2

External

XT1 input frequency

100

kHz

clock

(fXT)Note 1

XT1 input high-/

µs

low-level width

(tXTH, tXTL)

Notes 1.

The oscillation frequency and XT1 input frequency shown above indicate only oscillator characteristics.

Refer to AC Characteristics for instruction execution time.

The oscillation stabilization time is the time required to stabilize oscillation after VDD has been applied.

Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figure to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

•

Do not cross the wiring with the other signal lines.

•

Do not route the wiring near a signal line through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as VSS.

•

Do not ground the capacitor to a ground pattern through which a high current flows.

•

Do not fetch signals from the oscillator.

The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

XT1

XT2

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