UPD750064CU datasheet(39/82 Pages) NEC

39 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Table 9-1. Status of Each Hardware After Reset (1/2)

Hardware

RESET Signal Generation

in Standby Mode

in Operation

Program counter (PC)

µPD750064 Sets the low-order 4 bits of

Sets the low-order 4 bits of

program memory’s address

0000H to the PC11 to PC8 and

the contents of address 0001H

to the PC7 to PC0.

µPD750066, Sets the low-order 5 bits of

Sets the low-order 5 bits of

750068

program memory’s address

0000H to the PC12 to PC8 and

the contents of address 0001H

to the PC7 to PC0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0 to SK2)

Interrupt status flag (IST0, IST1)

Bank enable flag (MBE, RBE)

Sets the bit 6 of program

memory’s address 0000H to

the RBE and bit 7 to the MBE.

Stack pointer (SP)

Undefined

Stack bank select register (SBS)

1000B

Data memory (RAM)

Held

Undefined

General-purpose register (X, A, H, L, D, E, B, C)

Held

Undefined

Bank select register (MBS, RBS)

0, 0

Basic interval

Counter (BT)

Undefined

timer/watchdog

Mode register (BTM)

timer

Watchdog timer enable flag (WDTM)

Timer/event

Counter (T0)

counter (T0)

Modulo register (TMOD0)

FFH

Mode register (TM0)

TOE0, TOUT F/F

0, 0

Timer/event

Counter (T1)

counter (T1)

Modulo register (TMOD1)

FFH

Mode register (TM1)

TOE1, TOUT F/F

0, 0

Watch timer

Mode register (WM)

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