UPD750064CU datasheet(50/82 Pages) NEC

50 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Instruction

Number

Addressing

Mnemonic

Operand

of Machine

Operation

Skip Condition

Group

of Bytes

Cycles

Area

Branch

PCDE

µPD750064

PC11–0

← PC11-8+DE

µPD750066, 750068

PC12–0

← PC12-8+DE

PCXA

µPD750064

PC11–0

← PC11-8+XA

µPD750066, 750068

PC12–0

← PC12-8+XA

BCDE

µPD750064

PC11–0

← BCDENote 1

µPD750066, 750068

PC12–0

← BCDENote 2

BCXA

µPD750064

PC11–0

← BCXANote 1

µPD750066, 750068

PC12–0

← BCXANote 2

BRANote 3

µPD750064

*11

PC11–0

← addr1

µPD750066, 750068

PC12–0

← addr1

BRCB

!caddr

µPD750064

PC11–0

← caddr11–0

µPD750066, 750068

PC12–0

← PC12+caddr11–0

Subroutine

CALLANote 3

!addr1

µPD750064

*11

stack control

(SP–2)

← ×, ×, MBE, RBE

(SP–6) (SP–3) (SP–4)

← PC11–0

(SP–5)

← 0, 0, 0, 0

PC11–0

← addr1, SP ← SP–6

µPD750066, 750068

(SP–2)

← ×, ×, MBE, RBE

(SP–6) (SP–3) (SP–4)

← PC11–0

(SP–5)

← 0, 0, 0, PC12

PC12–0

← addr1, SP ← SP–6

Notes 1.

“0” must be set to B register.

Only low-order one bit is valid in B register.

The operations indicated with thick lines can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

UPD750064CU bảng dữ liệu(PDF) 50 Page - NEC

UPD750064CU bảng dữ liệu(HTML) 50 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

bảng dữ liệu tải về

Link URL