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RM0319 bảng dữ liệu(PDF) 356 Page - STMicroelectronics

tên linh kiện RM0319
Giải thích chi tiết về linh kiện  SPEAr320S architecture and functionality
PDF  368 Pages
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RM0319 bảng dữ liệu(HTML) 356 Page - STMicroelectronics

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DMA controller (DMAC)
RM0319
356/368
Doc ID 022640 Rev 3
36.4.1
How to operate single combined DMACINTR interrupt request signal
1.
Wait until the combined interrupt request from the DMAC (DMACINTR) goes active.
2.
Read the interrupt controller status register and determine whether the source of the
request was the DMAC.
3.
Read the DMACIntStatus register to determine the DMA channel that generated the
interrupt. If more than one request is active (that is, more than one bit are set in the
IntStatus field), it is recommended to check the highest priority channels first (0, 1, 2
and so on).
4.
Read the DMACIntTCStatus register to determine whether the interrupt was generated
because of the end of the transfer or because an error occurred. If the bit
corresponding to the DMA channel (from step #3) in the field IntTCStatus is set, the
data transfer has been completed
› step #6.
5.
Read the DMACIntErrStatus register to determine whether the interrupt was generated
because of the end of the transfer or because an error occurred. If the bit
corresponding to the DMA channel (from step #3) in the field IntErrorStatus is set, an
error occurred
› step #6
6.
Set the relevant bit in the DMACIntTCClear register or in the DMACIntErrClr register,
respectively, to clear the interrupt request.



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