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RM0319 bảng dữ liệu(PDF) 30 Page - STMicroelectronics

tên linh kiện RM0319
Giải thích chi tiết về linh kiện  SPEAr320S architecture and functionality
PDF  368 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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RM0319 bảng dữ liệu(HTML) 30 Page - STMicroelectronics

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Multilayer interconnect matrix (BUSMATRIX)
RM0319
30/368
Doc ID 022640 Rev 3
4
Multilayer interconnect matrix (BUSMATRIX)
This chapter focuses on BUSMATRIX functionality and operation.
For technical details about the programmable registers related to the BUSMATRIX, refer to
the system configuration registers (MISC) in the following companion document:
●
RM0321: SPEAr320S address map and registers
4.1
Overview
The internal architecture is based on several shared subsystem logics interconnected
through a multilayer interconnection matrix, shown in Figure 3.
The BUSMATRIX has 7 master inputs: two DMA inputs, and one input each for the CPU,
Reconfigurable Array Subsystem (RAS) block, Ethernet controller, USB controllers and C3.
There are 10 slave outputs connected to almost all the system blocks: low speed
subsystem, application subsystem, basic subsystem, high speed subsystem, RAS and
MPMC DDR memory controller ports.



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