RM0319 datasheet(28/368 Pages) STMICROELECTRONICS

28 / 368 page

ARM926EJ-S

RM0319

28/368

Doc ID 022640 Rev 3

The MMU features are:

●

Standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access

protection scheme

●

Mapping sizes are 1 MB (sections), 64 KB (large pages), 4 KB (small pages), and 1 KB

(tiny pages)

●

Access permissions for large pages and small pages can be specified separately for

each quarter of the page (subpage permissions).

●

Hardware page table walks

●

Invalidate entire TLB using CP15 c8

●

Invalidate TLB entry selected by MVA, using CP15 c8

●

Lockdown of TLB entries using CP15 c10

3.3.2

Caches and write buffer

The ARM926EJ-S processor includes:

●

a 16-KB instruction cache (ICache)

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a 16-KB data cache (DCache)

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a 16-KB write buffer

The caches have the following features:

●

Virtual index, virtual tag, addressed using the Modified Virtual Address (MVA)

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Four-way set associative, with a cache line length of 32 bytes per line, and with two

dirty bits in the DCache.

●

DCache supports write-through and write-back (or copyback) cache operations,

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Allocate on read-miss is supported. The caches perform critical-word first cache

refilling.

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Pseudo-random or round-robin replacement selectable

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Cache lockdown registers enable control over which cache ways are used for allocation

on a linefill, providing a mechanism for both lockdown and controlling cache pollution.

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The DCache stores the physical address (PA) tag.

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PLD data preload instruction does not cause data cache linefills.

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Maintenance operations to provide efficient invalidation of the entire DCache or

ICache, regions of the two caches or region of virtual memory.

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Provide operations for efficient cleaning and invalidation of entire DCache, regions of it

and regions of virtual memory.

The latter enables DCache coherency to be efficiently maintained when small code changes

occur, for example for self-modifying code and changes to exception vectors.

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