RM0319 datasheet(353/368 Pages) STMICROELECTRONICS

353 / 368 page

RM0319

DMA controller (DMAC)

Doc ID 022640 Rev 3

353/368

Table 124.

DMAC signal interface

36.3.2

AHB slave interface

The AHB slave interface block allows to connect the DMAC to the AMBA AHB bus.

In particular, the AHB slave interface properly decodes read and write commands on the

AHB bus providing access to DMAC memory-mapped registers for configuration purposes.

It is worth mentioning that the AHB slave and the two AHB masters use the same clock,

HCLK, which means that they are all synchronous.

36.3.3

AHB master interfaces

The DMAC contains two full independent AHB masters for data transfer. This feature allows,

for example, DMAC to transfer data directly from the memory connected to AHB port #1 to

any AHB peripheral connected to AHB port #2. Besides, it enables transactions between the

DMAC and any APB peripheral to occur independently of transactions on AHB bus 1.

Each AHB master is capable of dealing with all types of AHB transactions, including:

●

Split, retry and error responses from AHB slaves. If a peripheral performs a split or

retry, the DMAC stalls and waits until the transaction can complete.

●

Locked transfers for source and destination of each stream.

●

Setting of protection bits for transfers on each stream.

The two AHB masters are connected to buses of the same width (the default is a 32-bit bus).

However, source and destination transfers can be with different widths, and can be the same

width or narrower than the physical bus width. In this case, the DMAC packs or unpacks

data as appropriate.

Group

Signal name

Direction

Size

(bit)

Description

DMA request

DMACBREQ

Input

DMA burst transfer request

DMACLBREQ

Input

DMA last burst transfer request

DMACSREQ

Input

DMA single transfer request

DMACLSREQ

Input

DMA last single transfer request

DMA response

DMACCLR

Output

DMA request clear

DMACTC

Output

DMA terminal count (transaction complete)

Interrupt

request

DMACINTERR

Output

DMA error interrupt request

DMACINTTC

Output

DMA terminal count interrupt request

DMACINTR

Output

DMA interrupt request. This signal

combines the DMACINTERR and

DMACINTTC requests.

AHB Master #1 -

Input/Output -

See AMBA specification

AHB Master #2 -

Input/Output -

See AMBA specification

AHB Slave

Input/Output -

See AMBA specification

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