RM0319 datasheet(282/368 Pages) STMICROELECTRONICS

282 / 368 page

LCD display controller (CLCD)

RM0319

282/368

Doc ID 022640 Rev 3

24.6.1

CLCDMBEINTR

The master bus error interrupt is asserted when an ERROR response is received by the

master interface during a transaction with a slave. When such an error is encountered, the

master interface enters an error state and remains in this state until clearance of the error

has been signalled to it. On completion of the respective interrupt service routine, the

master bus error interrupt can be cleared by writing a logic ‘1’ to the MBERROR bit within

the LCDICR Register. This action releases the master interface from its ERROR state to the

start of FRAME state, enabling a fresh frame of data display to be initiated.

24.6.2

LCDVCOMPINTR

The vertical compare interrupt is asserted when one of four vertical display regions,

selected using the Control Register, is reached. The interrupt can occur at the start of:

●

vertical synchronization

●

back porch

●

active video

●

front porch

It is possible to clear the interrupt by writing a logic ‘1’ to the VComp bit in the LCDICR

24.6.3

CLCDLNBUINTR

The LCD next base address update interrupt is asserted when either the LCDUPBASE or

the LCDLPBASE values are transferred to the LCDUPCURR or LCDLPCURR incrementors

respectively. This signals to the system that it is safe to update the LCDUPBASE or the

LCDLPBASE Registers with new frame base addresses if required.

It is possible to clear the interrupt by writing a logic ‘1’ to the LNBU bit in the LCDICR

24.6.4

CLCDFUFINTR

The FIFO underflow interrupt is asserted when internal data is requested from an empty

DMA FIFO. Internally, individual upper and lower panel DMA FIFO underflow interrupt

signals are generated and CLCDFUFINTR is the single combined version of these ones.

It is possible to clear the interrupt by writing a logic ‘1’ to the FUF bit in the LCDICR register.

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