RM0319 datasheet(281/368 Pages) STMICROELECTRONICS

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RM0319

LCD display controller (CLCD)

Doc ID 022640 Rev 3

281/368

24.4.11

Bus architecture

The CLCD incorporates a master and a slave interface.

The master interface is directly connected to a memory controller with an AMBA AHB slave

interface, while the slave interface is connected to the AMBA AHB bus.

AMBA AHB supports a wide range of on-chip bus sizes, from eight bits up to 1 024 bits. The

CLCD master and slave interfaces are implemented as 32 bit data bus devices only.

24.5

Clocks

The CLCDCLK for the CLCD IP can be input from 2 sources. LCD Timing Register2 selects

between HCLK and 48MHz clock.

Figure 97.

CLCD clock muxing scheme

24.6

Interrupts

There are five interrupts generated by the CLCD. The following are individual maskable

active HIGH interrupts:

●

CLCDMBEINTR

●

CLCDVCOMPINTR

●

CLCDLNBUINTR

●

CLCDFUFINTR

The output is a single combined interrupt: CLCDINTR. Each of the four individual maskable

interrupts is enabled or disabled by changing the mask bits in the LCDIMSC Register. The

status of the individual interrupt sources can be read from the LCDRIS Register.

48 MHz

DMA FIFO

LCD Control

LCD Panel

Palete RAM

CLCDCLK

HCLK

CLCDCLKSEL

System Frame

Buffer Memory

AHB Master only

Interface bus for DMA

AHB Slave only Interface bus for

Controller programming

CLCD Controller

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