RM0319 datasheet(174/368 Pages) STMICROELECTRONICS

174 / 368 page

Fast Ethernet ports (RMII0/RMII1/MII1)

RM0319

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Doc ID 022640 Rev 3

13.6.2

Enabling the RMII interface

Enable RMII in "Extended" mode

write 0x1 to bit [0] in the RASCFG Extended Control Register (0xB3000018)

For RMII0: write 0x1 to bits [17:16] in the RASCFG Extended Control Register

(0xB3000018)

For RMII1: write 0x1 to bits [19:18] in the RASCFG Extended Control Register

(0xB3000018)

Configure the RASCFG "IP Port select for GPIO_x to GPIO_y in Extended Mode”

registers (0xB30000A4 - 0xB30000CC)

Go to Initializing and configuring MACB on page 174

13.6.3

Initializing and configuring MACB

The initialization of the MACB configuration (for example. loop-back mode, frequency ratios)

must be done while transmit and receive circuits are disabled. See the description of the

network control register and network configuration register earlier in this document.

The size of the system memory is 1GB and the address range is from (0x0000_0000 -

0x3FFF_FFFF). The DMA interface (AHB Master) can access this space to store the

transmit and receive buffers and queues.

To change loop-back mode, follow these steps:

Write to network control register to disable transmit and receive circuits.

Write to network control register to change loop-back mode.

Write to network control register to re-enable transmit or receive circuits.

Note:

These writes to network control register cannot be combined in any way.

13.6.4

Creating a receive buffer list

Receive data is written to areas of data (buffers) in the system memory. These buffers are

listed in another data structure that also resides in the main memory. This data structure

(receive buffer queue) is a sequence of descriptor entries as defined in receive buffer

descriptor entry. It points to this data structure:

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