RM0319 datasheet(104/368 Pages) STMICROELECTRONICS

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External memory interface (EMI)

RM0319

104/368

Doc ID 022640 Rev 3

External memory interface (EMI)

This chapter focuses on EMI functionality and operation.

For technical details about the programmable registers related to the EMI, refer to the EMI

registers in the following companion document:

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RM0321: SPEAr320S address map and registers

9.1

Overview

The EMI Controller provides a simple external memory interface that can be used to

connect to SRAM, NOR Flash memory or FPGA devices. The protocol uses quite a few

signals. This block is designed to perform simple read-write operations and does not

support any kind of burst operation (neither on the AHB nor on the EMI interface). The data

exchange flow of the attached device must be broken down into simple operations and

should be performed in accordance with the EMI cycles

9.2

Main features

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AHB slave interface

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Non-multiplexed address and data bus

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EMI is always master on the EMI bus

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Performs 16-/8-bit transfers

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Can access 4 different peripherals using CS#, one at a time

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Support single transfer with acknowlegement signal expected which is used to

terminate the transfer

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Supports peripherals which use the byte lane procedure

9.3

Functional description

The EMI block is an AHB slave module which can interface an external FPGA,SRAM or

NOR Flash through the EMI interface. The following figure shows the AHB and EMI

interfaces of the EMI module.

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