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RM0319 bảng dữ liệu(PDF) 103 Page - STMicroelectronics |
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RM0319 bảng dữ liệu(HTML) 103 Page - STMicroelectronics |
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103 / 368 page  RM0319 Parallel NAND Flash controller (FSMC) Doc ID 022640 Rev 3 103/368 Attribute memory space access The only difference with respect to common memory space access mode is that the timings used are specified in the register GenMemCtrl_Attrib. In practice, this secondary access works exactly the same as common memory space accesses, but this can be used to implement a functionality that is needed in some (but not all) NAND Flash memories. Some Flash memories require that after writing the last part of the address, the controller has to wait and check that R/B (the wait signal from the Flash) goes low. This pre-wait time can be up to 100ns, then if there is such event the controller has to wait again until R/B goes high. During all this period CE must be held low. Other NAND Flash memories (such as the Samsung 1Gbit) do not require the pre-wait time; they just require that when the memory is being accessed and R/B is low, the controller should wait until R/B goes high. |
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