PM0214 datasheet(42/245 Pages) STMICROELECTRONICS

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The Cortex-M4 processor

PM0214

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DocID022708 Rev 4

stack frame is the same as that of ARMv7-M implementations without an FPU. Figure 12 on

page 42 shows this stack frame also.

Figure 12. Cortex-M4 stack frame layout

Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.

The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration

Control Register (CCR).

The stack frame includes the return address. This is the address of the next instruction in

the interrupted program. This value is restored to the PC at exception return so that the

interrupted program resumes.

In parallel to the stacking operation, the processor performs a vector fetch that reads the

exception handler start address from the vector table. When stacking is complete, the

processor starts executing the exception handler. At the same time, the processor writes an

EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack

frame and what operation mode the was processor was in before the entry occurred.

If no higher priority exception occurs during exception entry, the processor starts executing

the exception handler and automatically changes the status of the corresponding pending

interrupt to active.

If another higher priority exception occurs during exception entry, the processor starts

executing the exception handler for this exception and does not change the pending status

of the earlier exception. This is the late arrival case.

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