PM0214 datasheet(94/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

94/245

DocID022708 Rev 4

3.5.11

SHASX and SHSAX

Signed halving add and subtract with exchange / Signed halving subtract and add with

exchange.

Syntax

op{cond} {Rd}, Rn, Rm

where:

•

op is any of:

SHASX: Add and subtract with exchange and halving.

SHSAX: Subtract and add with exchange and halving.

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘Rd’ is the destination register

•

‘Rn’ is the register holding the operand

•

‘Rn’ ,‘Rm’ are the registers holding the first and second operands

Operation

The SHASX instruction:

Adds the top halfword of the first operand with the bottom halfword of second operand.

Writes the halfword result of the addition to the top halfword of the destination register,

shifted by one bit to the right causing a divide by two, or halving.

Subtracts the top halfword of second operand from bottom highword of first operand.

Writes the halfword result of the division in the bottom halfword of the destination

The SHSAX instruction:

Subtracts the bottom halfword of second operand from top highword of first operand.

Writes the halfword result of the addition to the bottom halfword of the destination

Adds the bottom halfword of the first operand with the top halfword of second operand.

Writes the halfword result of the division in the top halfword of the destination register,

shifted by one bit to the right causing a divide by two, or halving.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

Examples

SHASX

R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2

; and writes halved result to top halfword of R7

; Subtracts top halfword of R2 from bottom halfword of

; R4 and writes halved result to bottom halfword of R7

SHSAX

R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword

; of R3 and writes halved result to top halfword of R0

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