PM0214 datasheet(223/245 Pages) STMICROELECTRONICS

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DocID022708 Rev 4

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PM0214

Core peripherals

244

4.4.12

Bus fault status register (BFSR)

Bit 15

BFARVALID: Bus Fault Address Register (BFAR) valid flag. The processor sets this bit to 1

after a bus fault where the address is known. Other faults can set this bit to 0, such as a

memory management fault occurring later.

If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler

must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler

whose BFAR value has been overwritten.

0: Value in BFAR is not a valid fault address

1: BFAR holds a valid fault address.

Bit 14

Reserved, must be kept cleared

Bit 13

LSPERR: Bus fault on floating-point lazy state preservation.

0: No bus fault occurred during floating-point lazy state preservation.

1: A bus fault occurred during floating-point lazy state preservation

Bit 12

STKERR: Bus fault on stacking for exception entry. When the processor sets this bit to 1, the

SP is still adjusted but the values in the context area on the stack might be incorrect. The

processor does not write a fault address to the BFAR.

0: No stacking fault

1: Stacking for an exception entry has caused one or more bus faults.

Bit 11

UNSTKERR: Bus fault on unstacking for a return from exception. This fault is chained to the

handler. This means that when the processor sets this bit to 1, the original return stack is still

present. The processor does not adjust the SP from the failing return, does not performed a

new save, and does not write a fault address to the BFAR.

0: No unstacking fault

1: Unstack for an exception return has caused one or more bus faults.

Bit 10

IMPRECISERR: Imprecise data bus error. When the processor sets this bit to 1, it does not

write a fault address to the BFAR. This is an asynchronous fault. Therefore, if it is detected

when the priority of the current process is higher than the bus fault priority, the bus fault

becomes pending and becomes active only when the processor returns from all higher priority

processes. If a precise fault occurs before the processor enters the handler for the imprecise

bus fault, the handler detects both IMPRECISERR set to 1 and one of the precise fault status

bits set to 1.

0: No imprecise data bus error

1: A data bus error has occurred, but the return address in the stack frame is not related to

the instruction that caused the error.

Bit 9

PRECISERR: Precise data bus error. When the processor sets this bit is 1, it writes the faulting

address to the BFAR.

0: No precise data bus error

1: A data bus error has occurred, and the PC value stacked for the exception return points to

the instruction that caused the fault.

Bit 8

IBUSERR: Instruction bus error. The processor detects the instruction bus error on prefetching

an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting

instruction.

When the processor sets this bit is 1, it does not write a fault address to the BFAR.

0: No instruction bus error

1: Instruction bus error.

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