PM0214 datasheet(208/245 Pages) STMICROELECTRONICS

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Core peripherals

PM0214

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DocID022708 Rev 4

4.4.2

CPUID base register (CPUID)

Address offset: 0x00

Reset value: 0x410F C241

Required privilege: Privileged

The CPUID register contains the processor part number, version, and implementation

information.

Bit 2

DISFOLD

Disables folding of IT instructions:

0: Enables IT instructions folding.

1: Disables IT instructions folding.

In some situations, the processor can start executing the first instruction in an IT block while it

is still executing the IT instruction. This behavior is called IT folding, and improves

performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the

DISFOLD bit to 1 before executing the task, to disable IT folding.

Bit 1

DISDEFWBUF

This bit only affects write buffers implemented in the Cortex-M4 processor.

Disables write buffer use during default memory map accesses: This causes all BusFaults to

be precise BusFaults but decreases performance because any store to memory must

complete before the processor can execute the next instruction.

0: Enable write buffer use: stores to memory is competed before next instruction.

1: Disable write buffer use.

Bit 0

DISMCYCINT

Disables interrupt of multi-cycle instructions. When set to 1, disables interruption of load

multiple and store multiple instructions. This increases the interrupt latency of the processor

because any LDM or STM must complete before the processor can stack the current state and

enter the interrupt handler.

0: Enable interruption latency of the processor (load/store and multiply/divide operations).

1: Disable interruptions latency.

3029

Implementer

Variant

Constant

rrrr

PartNo

Revision

rrrr

Bits 31:24

Implementer: Implementer code

0x41: ARM

Bits 23:20

Variant: Variant number

The r value in the rnpn product revision identifier

0x0: revision 0

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