PM0214 datasheet(172/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

172/245

DocID022708 Rev 4

3.11.3

DMB

Data memory barrier.

Syntax

DMB{cond}

where: ‘cond’ is an optional condition code, see Conditional execution on page 64.

Operation

DMB acts as a data memory barrier. It ensures that all explicit memory accesses that

appear, in program order, before the DMB instruction are completed before any explicit

memory accesses that appear, in program order, after the DMB instruction. DMB does not

affect the ordering or execution of instructions that do not access memory.

Condition flags

This instruction does not change the flags.

Examples

DMB

; Data Memory Barrier

3.11.4

DSB

Data synchronization barrier.

Syntax

DSB{cond}

where: ‘cond’ is an optional condition code, see Conditional execution on page 64.

Operation

DSB acts as a special data synchronization memory barrier. Instructions that come after the

DSB, in program order, do not execute until the DSB instruction completes. The DSB

instruction completes when all explicit memory accesses before it complete.

Condition flags

This instruction does not change the flags.

Examples

DSB ; Data Synchronisation Barrier

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