PM0214 datasheet(167/245 Pages) STMICROELECTRONICS

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PM0214

The STM32 Cortex-M4 instruction set

244

3.10.26

VSQRT

Floating-point Square Root.

Syntax

VSQRT{cond}.F32 Sd, Sm

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

‘Sd’ is the destination floating-point value

•

‘Sm’ is the operand floating-point value.

Operation

This instruction:

Calculates the square root of the value in a floating-point register.

Writes the result to another floating-point register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

3.10.27

VSTM

Floating-point Store Multiple.

Syntax

VSTM{mode}{cond}{.size} Rn{!}, list

where:

•

‘mode’ is the addressing mode:

IA Increment After. The consecutive addresses start at the address specified in Rn.

This is the default and can be omitted.

DB Decrement Before. The consecutive addresses end just before the address

specified in Rn.

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

‘size’ is an optional data size specifier. If present, it must be equal to the size in bits, 32

or 64, of the registers in list.

•

‘Rn’ is the base register. The SP can be used.

•

‘!’ is the function that causes the instruction to write a modified value back to Rn.

Required if mode == DB.

•

‘list’ is a list of the extension registers to be stored, as a list of consecutively numbered

doubleword or singleword registers, separated by commas and surrounded by

brackets.

Operation

This instruction stores multiple extension registers to consecutive memory locations using a

base address from an ARM core register.

Restrictions

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