PM0214 datasheet(162/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

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DocID022708 Rev 4

3.10.18

VMOV ARM Core register to scalar

Transfers one word to a floating-point register from an ARM core register.

Syntax

VMOV{cond}{.32} Dd[x], Rt

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

32 is an optional data size specifier.

•

Dd[x] is the destination, where [x] defines which half of the doubleword is transferred,

as follows:

If x is 0, the lower half is extracted

If x is 1, the upper half is extracted.

•

Rt is the source ARM core register.

Operation

This instruction transfers one word to the upper or lower half of a doubleword floating-point

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

3.10.19

VMRS

Move to ARM Core register from floating-point System Register.

Syntax

VMRS{cond} Rt, FPSCR

VMRS{cond} APSR_nzcv, FPSCR

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

‘Rt’ is the destination ARM core register. This register can be R0-R14.

•

‘APSR_nzcv’ Transfer floating-point flags to the APSR flags.

Operation

This instruction performs one of the following actions:

Copies the value of the FPSCR to a general-purpose register.

Copies the value of the FPSCR flag bits to the APSR N, Z, C, and V flags.

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions optionally change the flags: N, Z, C, V

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