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PM0020 bảng dữ liệu(PDF) 65 Page - STMicroelectronics |
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PM0020 bảng dữ liệu(HTML) 65 Page - STMicroelectronics |
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65 / 87 page ![]() PM00020 ISC logic description 65/87 12.4.3 IDcode register 12.4.4 Usercode register 12.4.5 MFG register Bit 2 READY/BUSY: Ready/Busy status bit 0: Busy* 1: Ready This bit goes low 1us after an internal ERASE, PROGRAM, READ, or BLANK CHECK operation is initiated. The polling loop which checks busy status, for PROGRAM or ERASE operations, must not begin before the 1us delay. This will avoid a false end of operation status. BUSY status should be polled to determine when any operation on the Flash is over. Bits 1:0 ISC_ERROR: These bits comply with IEEE 1532 standard. The ISC Error bits indicate the ISC status of the previously executed instruction. They are updated any time a new instruction is loaded. The ISC Error bits indicate error only if an ISC instruction is loaded and the part is not in ISC mode. 00: N/A. 01: Error 10: Success (default) 11: N/A. 31 0 IDcode[31:0] rw Bits 31:0 IDCode 31 0 Usercode[31:0] rw Bits 31:0 Usercode 32 bits shift out only for USERCODE instruction 32 bits shift in of user code data for ISC_PROGRAM_UC instruction 31 0 MFG[31:0] rw Bits 31:0 Manufacturing information. Factory use only. |
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