AN3427 datasheet(31/52 Pages) STMICROELECTRONICS

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AN3427

Peripheral migration

Doc ID 019001 Rev 1

31/52

In this way, there can be no conflict between peripherals sharing the same I/O pin.

Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that

can be configured through the GPIOx_AFRL and GPIOx_AFRH registers:

–

After reset all I/Os are connected to the system’s alternate function 0 (AF0)

–

The peripherals’ alternate functions are mapped from AF1 to AF13

–

Cortex-M3 EVENTOUT is mapped on AF15

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate

functions mapped onto different I/O pins to optimize the number of peripheral I/O

functions for different device packages. For example, the USART2_RX pin can be

mapped on PA3 or PD6 pin

Note:

Please refer to the “Alternate function mapping” table in the STM32F20x and STM32F21x

datasheets for the detailed mapping of the system and peripherals’ alternate function I/O

pins.

Configuration procedure

–

Configure the desired I/O as an alternate function in the GPIOx_MODER register

–

Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively

–

Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

3.7

EXTI source selection

In STM32 F1 the selection of the EXTI line source is performed through the EXTIx bits in the

AFIO_EXTICRx registers, while in F2 series this selection is done through the EXTIx bits in

the SYSCFG_EXTICRx registers.

Only the mapping of the EXTICRx registers has been changed, without any changes to the

meaning of the EXTIx bits. However, the range of EXTIx bits values has been extended to

0b1000 to support the two ports added in F2, port H and I (in F1 series the maximum value

is 0b0110).

3.8

FLASH

The table below presents the difference between the FLASH interface in the STM32 F1 and

STM32 F2 series, these differences are the following:

●

New interface, new technology

●

New architecture, sectors instead of pages

●

New read protection mechanism, 3 read protection levels with JTAG fuse

As consequence the F2 Flash programming procedures and registers are different from the

the F1 series, i.e. any code on F1 series using the Flash needs to be rewritten to run on F2

series.

For more information on programming, erasing and protection of the F2 Flash memory,

please refer to the STM32F2xx Flash programming manual (PM0059).

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