AN3427 datasheet(17/52 Pages) STMICROELECTRONICS

17 / 52 page

AN3427

Peripheral migration

Doc ID 019001 Rev 1

17/52

PLL

– Connectivity line: main PLL

+ 2 PLLs for I2S, Ethernet

and OTG FS clock

– Other product lines: main

PLL

– Main PLL for system, OTG

FS, SDIO and RNG clock

– Dedicated PLL for I2S

clock

There is no change to PLL

enable/disable

RCC_CR[PLLON] and status

flag RCC_CR[PLLRDY].

However, PLL configuration

(clock source selection,

multiplication/division factors)

are different. In F2 series a

dedicated register

RCC_PLLCFGR is used to

configure the PLL parameters.

System clock

source

HSI, HSE or PLL

No change to SW configuration:

– Selection bits

RCC_CFGR[SW]

– Status flag RCC_CFGR[SWS]

System clock

frequency

up to 72 MHz depending on the

product line used

8 MHz after reset using HSI

120 MHz

16 MHz after reset using HSI

For STM32 F2, Flash wait states

must be adapted to the system

frequency depending on the

supply voltage range.

AHB

frequency

up to 72 MHz

up to 120 MHz

No change to SW configuration:

configuration bits

RCC_CFGR[HPRE]

APB1

frequency

up to 36 MHz

up to 30 MHz

No change to SW configuration:

configuration bits

RCC_CFGR[PPRE1].

In F2 series the PPRE1 bits

occupy bits [10:12], instead of

bits [8:10] in F1 series.

APB2

frequency

up to 72 MHz

up to 60 MHz

No change to SW configuration:

configuration bits

RCC_CFGR[PPRE2].

In F2 series the PPRE2 bits

occupy bits[13:15] of the

F1 series.

RTC clock

source

LSI, LSE or HSE/128

LSI, LSE or HSE clock

divided by 2 to 31

RTC clock source configuration

is done through the same bits

RCC_BDCR[RTCSEL] and

RCC_BDCR[RTCEN]. However,

in F2 series when HSE is

selected as RTC clock source,

additional bits are used in CFGR

to select the division factor to be

applied on HSE clock.

Table 4.

RCC differences between STM32 F1 and STM32 F2 series

RCC main

features

STM32 F1 series

STM32 F2 series

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