AN3427 datasheet(12/52 Pages) STMICROELECTRONICS

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Peripheral migration

AN3427

12/52

Doc ID 019001 Rev 1

3.2

System architecture

STM32 F2 series are a new generation on STM32 with significant improvement in features

and performance with outstanding results: 150DMIPS at 120MHz and execution from Flash

equivalent to 0-wait state performance.

3.2.1

32-bit multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all masters (CPU, DMA controllers, Ethernet,

USB HS) and slaves (Flash memory, 2 blocks of RAM, FSMC, AHB and APB peripherals)

and ensures seamless and efficient operation even when several high-speed peripherals

are working simultaneously. For instance, the core can access the Flash through the ART

Accelerator and the 112-Kbyte SRAM, while the DMA2 controller is transferring data from

the camera interface located on the AHB2 peripheral bus to an LCD connected to the

FSMC, and while the USB OTG High Speed interface is storing received data in the 16-

Kbyte SRAM block.

Figure 4.

STM32 F2 series system architecture

3.2.2

Adaptive real-time memory accelerator (ART Accelerator™)

To free the full performance of the Cortex-M3 core, ST has developed a leading-edge 90 nm

process and a unique technology, the adaptive real-time ART Accelerator™. To release the

processor full 150 DMIPS performance at this frequency, the accelerator implements an

instruction prefetch queue and branch cache which increases program execution speed

from the 128-bit Flash memory. Based on the CoreMark benchmark, the performance

achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from

Flash memory at a CPU frequency up to 120 MHz.

By default (after each device reset) the prefetch queue and branch cache are disabled, the

user can enable them using the PRFTEN, ICEN and DCEN bits in the FLASH_ACR register.

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