AN3427 datasheet(19/52 Pages) STMICROELECTRONICS

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AN3427

Peripheral migration

Doc ID 019001 Rev 1

19/52

Table 5. below provides an example of porting a system clock configuration from F1 to F2

series:

–

STM32F105/7 Connectivity Line running at maximum performance: system clock

at 72 MHz (PLL, clocked by the HSE, used as system clock source), Flash with 2

wait states and Flash prefetch queue enabled.

–

F2 series running at maximum performance: system clock at 120 MHz (PLL,

clocked by the HSE, used as system clock source), Flash with 3 wait states, Flash

prefetch queue and branch cache enabled.

As shown in the table below, only the Flash settings and PLL parameters (code in Bold

Italic) need to be rewritten to run on F2 series. However, HSE, AHB prescaler and system

clock source configuration are left unchanged, and the APB’s prescalers are adapted to the

maximum APB frequency in the F2 series.

Note:

The source code presented in the table below is intentionally simplified (time-out in wait loop

removed) and is based on the assumption that the RCC and Flash registers are at their

reset values.

For STM32F2xx you can use the clock configuration tool,

STM32F2xx_Clock_Configuration.xls, to generate a customized system_stm32f2xx.c file

containing a system clock configuration routine, that you adapt to your application

requirements. For more information, refer to AN3362 “Clock configuration tool for

STM32F2xx microcontrollers”

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