WM1811A datasheet(119/328 Pages) WOLFSON

119 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

119

CHARGE PUMP

The WM1811A incorporates a dual-mode Charge Pump which generates the supply rails for the

headphone output drivers, HPOUT1L and HPOUT1R.

The Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and

CPVOUTN according to the selected mode of operation.

The Charge Pump connections are illustrated in Figure 28 (see “Applications Information” for external

component values). An input decoupling capacitor may also be required at CPVDD, depending upon

the system configuration.

Figure 28 Charge Pump External Connections

The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the

output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to optimise

the power consumption according to the operating conditions. This can take two forms, which are

selected using the CP_DYN_PWR register bit.



Dynamic control (CP_DYN_PWR = 1)

Under Register control, the HPOUT1L_VOL and HPOUT1R_VOL register settings are used to control

the charge pump mode of operation.

Under Dynamic control, the audio signal level in the digital audio interface is used to control the

charge pump mode of operation. The CP_DYN_SRC_SEL register determines which of the digital

signal paths is used for this function - this may be the AIF1 DAC path or the AIF2 DAC path. The

CP_DYN_SRC_SEL should be set according to the active source for the HPOUT1L and HPOUT1R

outputs.

The Dynamic Charge Pump Control mode is the Wolfson ‘Class W’ mode, which allows the power

consumption to be optimised in real time, but can only be used if a single AIF source is the only signal

source. The Class W mode should not be used if any of the bypass paths are used to feed analogue

inputs into the output signal path, or if more than one AIF source is used to feed the headphone

output via the Digital Mixers.

The Charge Pump operating mode defaults to Register control; Dynamic control may be selected by

setting the CP_DYN_PWR register bit, if appropriate.

Note that the charge pump clock is derived from internal clock SYSCLK; either MCLK or the FLL

output selectable using the SYSCLK_SRC bit. Under normal circumstances an external clock signal

must be present for the charge pump to function. However, the FLL has a free-running mode that

does not require an external clock but will generate an internal clock suitable for running the charge

pump. The clock division from SYSCLK is handled transparently by the WM1811A without user

intervention, as long as SYSCLK and sample rates are set correctly. Refer to the “Clocking and

Sample Rates” section for more detail on the FLL and clocking configuration.

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