TMS470MF06607 datasheet(49/65 Pages) TI1

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TMS470MF06607

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SPNS157C

– JANUARY 2012

Table 5-17. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = output,

SPInSIMO = output, and SPInSOMI = input)(1)(2)(3)

(see Figure 5-15 and Figure 5-16)

NO.

MIN

MAX

UNIT

tc(SPC)M

Cycle time, SPICLK(4)

256tc(VCLK)

Pulse duration, SPICLK high

0.5tc(SPC)M - tr

0.5tc(SPC)M + 5

tw(SPCH)M

(clock polarity = 0)

2(5)

tw(SPCL)M

Pulse duration, SPICLK low (clock polarity = 1)

0.5tc(SPC)M - tf

0.5tc(SPC)M + 5

tw(SPCL)M

Pulse duration, SPICLK low (clock polarity = 0)

0.5tc(SPC)M - tf

0.5tc(SPC)M + 5

3(5)

Pulse duration, SPICLK high

0.5tc(SPC)M - tr

0.5tc(SPC)M + 5

tw(SPCH)M

(clock polarity = 1)

Delay time, SPISIMO data valid before

0.5tc(SPC)M - 15

td(SIMO-SPCH)M

SPICLK high (clock polarity = 0)

4(5)

Delay time, SPISIMO data valid before

0.5tc(SPC)M - 15

td(SIMO-SPCL)M

SPICLK low (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK

0.5tc(SPC)M - tr(SPC)

tv(SPCH-SIMO)M

high (clock polarity = 0)

5(5)

Valid time, SPISIMO data valid after SPICLK

0.5tc(SPC)M - tf(SPC)

tv(SPCL-SIMO)M

low (clock polarity = 1)

Setup time, SPISOMI before SPICLK high

tsu(SOMI-SPCH)M

(clock polarity = 0)

6(5)

Setup time, SPISOMI before SPICLK low

tsu(SOMI-SPCL)M

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK

th(SPCH-SOMI)M

high (clock polarity = 0)

7(5)

Hold time, SPISOMI data valid after SPICLK

th(SPCL-SOMI)M

low (clock polarity = 1)

(C2TDELAY+CSHOLD+

Setup time CS active until SPICLK high

2)*tc(VCLK)+0.5*tc(SPC)M -

(clock polarity = 0)

tf(SPICS) + tr(SPICLK)-6

tf(SPICS) + tr(SPICLK)+38

8(5)(6)

tC2TDELAY

(C2TDELAY+CSHOLD+

Setup time CS active until SPICLK low

2)*tc(VCLK)+0.5*tc(SPC)M -

(clock polarity = 1)

tf(SPICS) + tf(SPICLK)-6

tf(SPICS) + tf(SPICLK)+38

T2CDELAY*tc(VCLK) +

Hold time SPICLK low until CS inactive

tc(VCLK) - tf(SPICLK) +

(clock polarity = 0)

tr(SPICS)-28

tr(SPICS)+8

9(5)(6)

tT2CDELAY

T2CDELAY*tc(VCLK) +

Hold time SPICLK high until CS inactive

tc(VCLK) - tr(SPICLK) +

(clock polarity = 1)

tr(SPICS)-28

tr(SPICS)+8

10(7)

C2TDELAY * tc(VCLK) -

C2TDELAY * tc(VCLK)

tSPIENA

SPIENAn Sample Point

tf(SPICS)

(1)

he MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear.

(2)

tc(VCLK) = interface clock cycle time = 1 / f(VCLK).

(3)

For rise and fall timings, see Table 5-13.

(4)

When the SPI is in Master mode, the following must be true:

•

For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register

bits.

•

For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 90 ns.

(5)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6)

C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

(7)

C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

Peripheral Information and Electrical Specifications

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