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TMS470MF06607 bảng dữ liệu(PDF) 29 Page - Texas Instruments |
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TMS470MF06607 bảng dữ liệu(HTML) 29 Page - Texas Instruments |
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29 / 65 page ![]() TMS470MF06607 www.ti.com SPNS157C – JANUARY 2012 3.11.2 MBIST The TMS470M family supports memory built-in self test (MBIST) of the system and peripheral SRAM. The MBIST is accessible via the application in order to facilitate memory self test by the application by enabling the MBIST controllers associated with the specific RAMs to be tested. (For device-specific MBIST controller assignments, see Table 2-3.) The MBIST controller: • Supports testing of all system and peripheral RAM. • Captures the MBIST results in the MBIST status register (MSTFAIL). • Supports execution of each Memory BIST controller in parallel (MSINENA). For MSIENA bit assignments, see Table 2-3 • Supports execution of each Memory BIST controller individually (MSINENA). For MSIENA bit assignments, see Table 2-3 The MBIST controller selection is mapped to the MBIST controller/memory initialization enable register (MSIENA) within the SYS register frame. Each MBIST controller is enabled by setting the corresponding bit within this register and then enabling memory self-test via the memory self-test global enable within the global control register (MSTGCR.MSTGENA[3:0]). The MBIST controllers support execution of the following tests: • March13N, background 0 • March11N, background A • Checkerboard and Inverse Checkerboard • March13N, background 3, 0F, and 69 • PMOS Address decoder Algorithm • ROM2 algorithm for STC NOTE The algorithm to be applied is selectable via the memory self-test global control register algo selection field (MSTGCR.MBIST_ALGSEL[7:0]). Copyright © 2012, Texas Instruments Incorporated Device Configuration 29 Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 |
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