IO13PDB0V0 datasheet(185/197 Pages) MICROSEMI

185 / 197 page

SmartFusion Customizable System-on-Chip (cSoC)

Re vi s i on 12

6 - 3

Revision 10

(continued)

Corrected the Start-up time unit from "ms" to "µs" in Table 2-99 • Voltage Regulator

(SAR 39395).

2-86

Added the "References" section for "SmartFusion Development Tools" (SAR 43460).

3-1

Updated the "References" section for Programming (SAR 43304). Added the

"Application Notes on IAP Programming Technique" section (SAR 43458).

4-9

A note was added to the "Supply Pins" table, referring to the SmartFusion cSoC

Board Design Guidelines

application note for details on VCCPLLx capacitor

recommendations (SAR 42183).

5-1

In the "Supply Pins" section, the VPP capacitor value section has been modified to:

"For proper programming, 0.01μF, and 0.1μF to 1μF capacitors, (both rated at 16 V)

are to be connected in parallel across VPP and GND, and positioned as close to the

FPGA pins as possible." (SAR 43569).

5-1

In the "User-Defined Supply Pins" section, added description ’These pins are located

in Bank-2 (GPIO_16 to GPIO_31) for A2F060, A2F200, and A2F500 devices.’ for

GPIO_x (SAR 28595).

5-5

Updated the MAINXIN and MAINXOUT pin descriptions in the "Special Function Pins"

section to read "If an external RC network or clock input is used, the RC components

are connected to the MAINXIN pin, with MAINXOUT left floating. When the main

crystal oscillator is not being used, MAINXIN and MAINXOUT pins can be left

floating." (SAR 42807).

5-8

Live at Power-Up (LAPU) has been replaced with ’Instant On’.

Revision 9

(September 2012)

The number of signal conditioning blocks (SCBs) for A2F500 in the "SmartFusion

cSoC Family Product Table" was corrected to 4. Previously it had incorrectly been

listed as 2 (SAR 39536).

The "Product Ordering Codes" section was revised to clarify that only one eNVM size

for each device is currently available (SAR 40333).

Information pertaining to analog I/Os was added to the "Specifying I/O States During

Programming" section on page 1-3 (SAR 34836).

1-3

The formulas in the table notes for Table 2-29 • I/O Weak Pull-Up/Pull-Down

Resistances were corrected (SAR 34757).

2-27

Maximum values for VIL and VIH were corrected in LVPECL Table 2-66 • Minimum

and Maximum DC Input and Output Levels (SAR 37695).

2-43

Minimum pulse width High and Low values were added to the tables in the "Global

Tree Timing Characteristics" section. The maximum frequency for global clock

parameter was removed from these tables because a frequency on the global is only

an indication of what the global network can do. There are other limiters such as the

SRAM, I/Os, and PLL. SmartTime software should be used to determine the design

frequency (SAR 29270).

2-59

The temperature range for accuracy in Table 2-83 • Electrical Characteristics of the

RC Oscillator was changed from "0°C to 85°C" to "–40°C to 100°C" (SAR 33670). The

units for jitter were changed from ps to ps RMS (SAR 34270).

2-61

In Table 2-84 • Electrical Characteristics of the Main Crystal Oscillator, the output jitter

for the 10 MHz crystal was corrected from 50 ps RMS to 1 ns RS (SAR 32939).

Values for the startup time of VILXTAL were added (SAR 25248).

2-62

In Table 2-85 • Electrical Characteristics of the Low Power Oscillator, output jitter was

changed from 50 ps RMS to 30 ps RMS (SAR 32939). A value for ISTBXTAL standby

current was added (SAR 25249). Startup time for a test load of 30 pF was added

(SAR 27436).

2-62

Revision

Changes

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