SPC5644AF0MLU2 datasheet(19/138 Pages) FREESCALE

19 / 138 page

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

1.4.23

Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal

connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System.

Features include:

•

1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)

•

Memory controller supports various memory types

•

16-bit data bus, up to 22-bit address bus

•

Pin muxing supports 32-bit muxed bus

•

Selectable drive strength

•

Configurable bus speed modes

•

Bus monitor

•

Configurable wait states

1.4.24

Power management controller (PMC)

The power management controller contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V

supply with an external NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for

the 1.2 V supply, the 3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1) and the 5 V supply of the

regulators (VDDREG).

1.4.25

Nexus port controller

The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development support capabilities for the MPC5644A

Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins

and 12 pins are available in all packages.

1.4.26

JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001

standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant

with the IEEE 1149.1-2001 standard and supports the following features:

•

IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)

•

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

•

A 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

— ACCESS_AUX_TAP_ONCE

— ACCESS_AUX_TAP_eTPU

— ACCESS_CENSOR

•

3 test data registers to support JTAG Boundary Scan mode

— Bypass register

— Boundary scan register

— Device identification register

•

A TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

•

Censorship Inhibit Register

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