SPC5644AF0MLU2 datasheet(18/138 Pages) FREESCALE

18 / 138 page

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

•

Optional programmable watchdog window mode

•

Can optionally cause system reset or interrupt request on timeout

•

Reset by writing a software key to memory mapped register

•

Enabled out of reset

•

Configuration is protected by a software key or a write-once register

1.4.20

Cyclic redundancy check (CRC) module

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC features:

•

Support for CRC-16-CCITT (x25 protocol):

—X16 + X12 + X5 + 1

•

Support for CRC-32 (Ethernet protocol):

—X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

•

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

1.4.21

Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform

configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,

and information on platform memory errors reported by error-correcting codes and/or generic access error information for

certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes

these features:

•

Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented

•

For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the

MPC5644A.

The sources of the ECC errors are:

•Flash

•SRAM

•

Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM)

1.4.22

External bus interface (EBI)

The MPC5644A device features an external bus interface that is available in 324 TEPBGA and calibration packages.

The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz.

Customers running the device at 120 MHz or 132 MHz will use the /2 divider, giving an EBI frequency of 60 MHz or 66 MHz.

Customers running the device at 80 MHz will be able to use the /1 divider to have the EBI run at the full 80 MHz frequency.

Features include:

•

1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)

•

Memory controller with support for various memory types

•

16-bit data bus, up to 22-bit address bus

•

Pin muxing included to support 32-bit muxed bus

•

Selectable drive strength

•

Configurable bus speed modes

•

Bus monitor

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Configurable wait states

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