SPC5644AF0MLU2 datasheet(9/138 Pages) FREESCALE

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MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

•

Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to

report loss of lock conditions

•

Clock Quality Module

— Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected

— Detects the quality of the PLL output clock; if error detected, causes system reset or switches system clock to

crystal clock and causes interrupt request

•

Programmable interrupt request or system reset on loss of lock

•

Self-clocked mode (SCM) operation

1.4.7

SIU

The MPC5644A SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),

internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot

configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block

provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring

of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core

is via the crossbar switch. The SIU provides the following features:

•

System configuration

— MCU reset configuration via external pins

— Pad configuration control for each pad

— Pad configuration control for virtual I/O via DSPI serialization

•

System reset monitoring and generation

— Power-on reset support

— Reset status register provides last reset source to software

— Glitch detection on reset input

— Software controlled reset assertion

•

External interrupt

— Rising or falling edge event detection

— Programmable digital filter for glitch rejection

— Critical Interrupt request

— Non-Maskable Interrupt request

•GPIO

— Centralized control of I/O and bus pins

— Virtual GPIO via DSPI serialization (requires external deserialization device)

— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin

•

Internal multiplexing

— Allows serial and parallel chaining of DSPIs

— Allows flexible selection of eQADC trigger inputs

— Allows selection of interrupt requests between external pins and DSPI

1.4.8

Flash memory

The MPC5644A provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be

used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the

flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array

controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port,

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