SPC5644AF0MLU2 datasheet(93/138 Pages) FREESCALE

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MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

3.13

Configuring SRAM wait states

Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no

wait state is added.

Please see the device reference manual for details.

3.14

Platform flash controller electrical characteristics

3.15

Flash memory electrical characteristics

Table 31. Cutoff frequency for additional SRAM wait state

1 Max frequencies including 2% PLL FM.

SWSC Value

153

Table 32. APC, RWSC, WWSC settings vs. frequency of operation1,2

1 APC, RWSC and WWSC are fields in the flash memory BIUCR register used to

specify wait states for address pipelining and read/write accesses. Illegal

combinations exist—all entries must be taken from the same row.

2 TBD: To Be Defined.

Max. Flash Operating

Frequency (MHz)3

3 Max frequencies including 2% PLL FM.

APC4

4 APC must be equal to RWSC.

RWSC4

WWSC

20 MHz

0b000

0b11

61 MHz

0b001

0b11

90 MHz

0b010

0b11

123 MHz

0b011

0b11

153 MHz

0b100

0b11

Table 33. Flash program and erase specifications1

#Symbol

Parameter

Min.

Value

Typical

Value

Initial

Max2

Max3

Unit

1Tdwprogram CC P

Double Word (64 bits) Program Time

—

500

s

2Tpprogram CC P

Page Program Time

—

1604

500

s

3T16kpperase CC P

16 KB Block Pre-program and Erase

Time

—

270

1000

5000

5T64kpperase CC P

64 KB Block Pre-program and Erase

Time

—

800

1800

5000

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