SPC5644AF0MLU2 datasheet(15/138 Pages) FREESCALE

15 / 138 page

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI

can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are three identical

DSPI blocks on the MPC5644A MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS)

to improve high speed operation.

DSPI module features include:

•

Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and DSPI_C

•

3 sources of serialized data: eTPU_A, eMIOS output channels and memory-mapped register in the DSPI

•

4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external Interrupt input request,

memory-mapped register in the DSPI

•

32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the SIU to select either GPIO, eTPU

or eMIOS bits for serialization

•

The DSPI Module can generate and check parity in a serial frame

1.4.15

eSCI

Three enhanced serial communications interface (eSCI) modules provide asynchronous serial communications with peripheral

devices and other MCUs, and include support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block

provides the following features:

•

Full-duplex operation

•

Standard mark/space non-return-to-zero (NRZ) format

•

13-bit baud rate selection

•

Programmable 8-bit or 9-bit, data format

•

Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus

standard

•

Automatic parity generation

•

LIN support

— Autonomous transmission of entire frames

— Configurable to support all revisions of the LIN standard

— Automatic parity bit generation

— Double stop bit after bit error

— 10- or 13-bit break support

•

Separately enabled transmitter and receiver

•

Programmable transmitter output parity

•

2 receiver wake-up methods:

— Idle line wake-up

— Address mark wake-up

•

Interrupt-driven operation with flags

•

Receiver framing error detection

•

Hardware parity checking

•

1/16 bit-time noise detection

•

DMA support for both transmit and receive data

— Global error bit stored with receive data in system RAM to allow post processing of errors

1.4.16

FlexCAN

The MPC5644A MCU includes three controller area network (FlexCAN) blocks. The FlexCAN module is a communication

controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to

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