M95M02-DRMN6TP datasheet(23/41 Pages) STMICROELECTRONICS

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M95M02-DR

Instructions

In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte.

However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte

of input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address

counter are incremented. If more bytes are sent than will fit up to the end of the page, a

condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size

are overwritten from location 0 of the same page.

The instruction is not accepted, and is not executed, under the following conditions:

•

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before),

•

if a Write cycle is already in progress,

•

if the device has not been deselected, by driving high Chip Select (S), at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in),

•

if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Note:

The self-timed write cycle tW is internally executed as a sequence of two consecutive

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit

is read as “0” and a programmed bit is read as “1”.

Figure 13. Byte Write (WRITE) sequence

MS30905V1

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

High impedance

Instruction

24-bit address

765432

Data byte

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