M95M02-DRMN6TP datasheet(19/41 Pages) STMICROELECTRONICS

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M95M02-DR

Instructions

6.3.2

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write

Enable Latch is reset, and no Write or Write Status Register instruction is accepted.

The WEL bit is returned to its reset state by the following events:

•

Power-up

•

Write Disable (WRDI) instruction completion

•

Write Status Register (WRSR) instruction completion

•

Write (WRITE) instruction completion

6.3.3

BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be

software-protected against Write instructions. These bits are written with the Write Status

to 1, the relevant memory area (as defined in Table 2) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

6.3.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal enable the device to be put in the Hardware Protected mode (when the Status

mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits

and the Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4. Status Register format

SRWD

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

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