LCMXO2-640ZE-1TG100C datasheet(19/106 Pages) LATTICE

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2-15

Architecture

MachXO2 Family Data Sheet

PIO

The PIO contains three blocks: an input register block, output register block and tri-state register block. These

blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.

Table 2-8. PIO Signal List

Input Register Block

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condi-

tion high-speed interface signals before they are passed to the device core. In addition to this functionality, the input

Figure 2-12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2-13

shows the input register block for the PIOs on the right edge.

Left, Top, Bottom Edges

Input signals are fed from the sysIO buffer to the input register block (as signal D). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK).

If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay,

DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input

block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK)

by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to

sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.

Pin Name

I/O Type

Description

Input

Clock Enable

Input

Pin input from sysIO buffer.

INDD

Output

INCK

Output

Clock input

Output

DDR positive edge input

Output

Registered input/DDR negative edge input

Input

Output signal from the core (SDR and DDR)

Input

Output signal from the core (DDR)

Input

Tri-state signal from the core

Output

Data output signals to sysIO Buffer

Output

Tri-state output signals to sysIO Buffer

DQSR90

Input

DQS shift 90-degree read clock

DQSW90

Input

DQS shift 90-degree write clock

DDRCLKPOL

Input

DDR input register polarity control signal from DQS

SCLK

Input

System clock for input and output/tri-state blocks.

RST

Input

Local set reset signal

1. Available in PIO on right edge only.

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