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LCMXO2-640ZE-1TG100C bảng dữ liệu(PDF) 66 Page - Lattice Semiconductor |
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LCMXO2-640ZE-1TG100C bảng dữ liệu(HTML) 66 Page - Lattice Semiconductor |
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66 / 106 page  3-27 DC and Switching Characteristics MachXO2 Family Data Sheet Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered 9 tDVB Output Data Valid Before CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only 1.445 — 1.760 — 2.140 — ns tDVA Output Data Valid After CLK Output 1.445 — 1.760 — 2.140 — ns fDATA DDRX2 Serial Output Data Speed —280 —234 —194 Mbps fDDRX2 DDRX2 ECLK Frequency (minimum limited by PLL) —140 —117 — 97 MHz fSCLK SCLK Frequency — 70 — 59 — 49 MHz Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned 9 tDIA Output Data Invalid After CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only — 0.270 — 0.300 — 0.330 ns tDIB Output Data Invalid Before CLK Output — 0.270 — 0.300 — 0.330 ns fDATA DDRX4 Serial Output Data Speed —420 —352 —292 Mbps fDDRX4 DDRX4 ECLK Frequency — 210 — 176 — 146 MHz fSCLK SCLK Frequency — 53 — 44 — 37 MHz Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered 9 tDVB Output Data Valid Before CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only 0.873 — 1.067 — 1.319 — ns tDVA Output Data Valid After CLK Output 0.873 — 1.067 — 1.319 — ns fDATA DDRX4 Serial Output Data Speed —420 —352 —292 Mbps fDDRX4 DDRX4 ECLK Frequency (minimum limited by PLL) —210 —176 —146 MHz fSCLK SCLK Frequency — 53 — 44 — 37 MHz 7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1 9 tDVB Output Data Valid Before CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only. — 0.240 — 0.270 — 0.300 ns tDVA Output Data Valid After CLK Output — 0.240 — 0.270 — 0.300 ns fDATA DDR71 Serial Output Data Speed —420 —352 —292 Mbps fDDR71 DDR71 ECLK Frequency — 210 — 176 — 146 MHz fCLKOUT 7:1 Output Clock Frequency (SCLK) (minimum limited by PLL) —60—50 —42 MHz Parameter Description Device -3 -2 -1 Units Min. Max. Min. Max. Min. Max. |
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