LCMXO2-640ZE-1TG100C datasheet(67/106 Pages) LATTICE

67 / 106 page

3-28

DC and Switching Characteristics

MachXO2 Family Data Sheet

LPDDR

tDVADQ

Input Data Valid After DQS

Input

MachXO2-1200/U

and larger devices,

right side only.

—

0.349

—

0.381

—

0.396

tDVEDQ

Input Data Hold After DQS

Input

0.665

—

0.630

—

0.613

—

tDQVBS

Output Data Invalid Before

DQS Output

0.25

—

0.25

—

0.25

—

tDQVAS

Output Data Invalid After DQS

Output

0.25

—

0.25

—

0.25

—

fDATA

MEM LPDDR Serial Data

Speed

—

120

—

110

—

Mbps

fSCLK

SCLK Frequency

—

MHz

fLPDDR

LPDDR Data Transfer Rate

120

110

Mbps

DDR

tDVADQ

Input Data Valid After DQS

Input

MachXO2-1200/U

and larger devices,

right side only.

—

0.347

—

0.374

—

0.393

tDVEDQ

Input Data Hold After DQS

Input

0.665

—

0.637

—

0.616

—

tDQVBS

Output Data Invalid Before

DQS Output

0.25

—

0.25

—

0.25

—

tDQVAS

Output Data Invalid After DQS

Output

0.25

—

0.25

—

0.25

—

fDATA

MEM DDR Serial Data Speed

—

140

—

116

—

Mbps

fSCLK

SCLK Frequency

—

MHz

fMEM_DDR

MEM DDR Data Transfer Rate

N/A

140

N/A

116

N/A

Mbps

DDR2

tDVADQ

Input Data Valid After DQS

Input

MachXO2-1200/U

and larger devices,

right side only.

—

0.372

—

0.394

—

0.410

tDVEDQ

Input Data Hold After DQS

Input

0.690

—

0.658

—

0.618

—

tDQVBS

Output Data Invalid Before

DQS Output

0.25

—

0.25

—

0.25

—

tDQVAS

Output Data Invalid After DQS

Output

0.25

—

0.25

—

0.25

—

fDATA

MEM DDR Serial Data Speed

—

140

—

116

—

Mbps

fSCLK

SCLK Frequency

—

MHz

fMEM_DDR2

MEM DDR2 Data Transfer

Rate

N/A

140

N/A

116

N/A

Mbps

Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other

operating conditions, including industrial, can be extracted from the Diamond software.

General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.

Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).

DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.

7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).

For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03ns)/2.

The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 167ps (-3), 182ps (-2), 195ps (-1).

This number for general purpose usage. Duty cycle tolerance is +/-10%.

Duty cycle is +/- 5% for system usage.

10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.

Parameter

Description

Device

-3

-2

-1

Units

Min.

Max.

Min.

Max.

Min.

Max.

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