LCMXO2-640ZE-1TG100C datasheet(71/106 Pages) LATTICE

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DC and Switching Characteristics

MachXO2 Family Data Sheet

tROTATE_WD

PHASESTEP Pulse Width

—

VCO Cycles

1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over

1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.

3. Using LVDS output buffers.

4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See TN1199, MachXO2 sysCLOCK PLL

Design and Usage Guide for more details.

5. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.

6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be

transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table.

7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default

value of none.

8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence

of SSO noise.

sysCLOCK PLL Timing (Continued)

Over Recommended Operating Conditions

Parameter

Descriptions

Conditions

Min.

Max.

Units

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