LCMXO2-640ZE-1TG100C datasheet(61/106 Pages) LATTICE

61 / 106 page

3-22

DC and Switching Characteristics

MachXO2 Family Data Sheet

LPDDR

tDVADQ

Input Data Valid After DQS

Input

MachXO2-1200/U and

larger devices, right

side only.

—

0.369

—

0.395

—

0.421

tDVEDQ

Input Data Hold After DQS

Input

0.529

—

0.530

—

0.527

—

tDQVBS

Output Data Invalid Before

DQS Output

0.25

—

0.25

—

0.25

—

tDQVAS

Output Data Invalid After DQS

Output

0.25

—

0.25

—

0.25

—

fDATA

MEM LPDDR Serial Data

Speed

—

280

—

250

—

208

Mbps

fSCLK

SCLK Frequency

—

140

—

125

—

104

MHz

fLPDDR

LPDDR Data Transfer Rate

280

250

208

Mbps

DDR

tDVADQ

Input Data Valid After DQS

Input

MachXO2-1200/U and

larger devices, right

side only.

—

0.350

—

0.387

—

0.414

tDVEDQ

Input Data Hold After DQS

Input

0.545

—

0.538

—

0.532

—

tDQVBS

Output Data Invalid Before

DQS Output

0.25

—

0.25

—

0.25

—

tDQVAS

Output Data Invalid After DQS

Output

0.25

—

0.25

—

0.25

—

fDATA

MEM DDR Serial Data Speed

—

300

—

250

—

208

Mbps

fSCLK

SCLK Frequency

—

150

—

125

—

104

MHz

fMEM_DDR

MEM DDR Data Transfer Rate

N/A

300

N/A

250

N/A

208

Mbps

DDR2

tDVADQ

Input Data Valid After DQS

Input

MachXO2-1200/U and

larger devices, right

side only.

—

0.360

—

0.378

—

0.406

tDVEDQ

Input Data Hold After DQS

Input

0.555

—

0.549

—

0.542

—

tDQVBS

Output Data Invalid Before

DQS Output

0.25

—

0.25

—

0.25

—

tDQVAS

Output Data Invalid After DQS

Output

0.25

—

0.25

—

0.25

—

fDATA

MEM DDR Serial Data Speed

—

300

—

250

—

208

Mbps

fSCLK

SCLK Frequency

—

150

—

125

—

104

MHz

fMEM_DDR2

MEM DDR2 Data Transfer

Rate

N/A

300

N/A

250

N/A

208

Mbps

Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other

operating conditions, including industrial, can be extracted from the Diamond software.

General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.

Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).

DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.

7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).

For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03ns)/2.

The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 105ps (-6), 113ps (-5), 120ps (-4).

This number for general purpose usage. Duty cycle tolerance is +/-10%.

Duty cycle is +/- 5% for system usage.

10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.

Parameter

Description

Device

-6

-5

-4

Units

Min.

Max.

Min.

Max.

Min.

Max.

LCMXO2-640ZE-1TG100C bảng dữ liệu(PDF) 61 Page - Lattice Semiconductor

LCMXO2-640ZE-1TG100C bảng dữ liệu(HTML) 61 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL