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ST10F280 bảng dữ liệu(PDF) 210 Page - STMicroelectronics |
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ST10F280 bảng dữ liệu(HTML) 210 Page - STMicroelectronics |
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210 / 239 page ![]() Electrical characteristics ST10F280 210/239 Doc ID 8673 Rev. 3 A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fastest conversion rate = 4.85μs at 40MHz). This time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. 20.4 AC characteristics 20.4.1 Test waveforms Figure 75. Input / output waveforms Figure 76. Float waveforms 20.4.2 Definition of internal timing The internal operation of the ST10F280 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL”. The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F280. The example for PLL operation shown in Figure 73 refers to a PLL factor of 4. |
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