ST10F280_12 datasheet(28/239 Pages) STMICROELECTRONICS

tên linh kiện	ST10F280

Giải thích chi tiết về linh kiện	16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM

PDF	239 Pages

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

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Memory organization

ST10F280

28/239

Doc ID 8673 Rev. 3

bit data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at

40MHz CPU clock. No tristate waitstate is used.

XPORT9, XTIMER, XPORT10, XADCMUX: Address range 00’C000h 00’C3FFh is reserved

for the XPORT9, XPORT10, XTIMER and XADCMUX peripherals access. The XPORT9,

XTIMER, XPORT10, XADCMUX are enabled by setting XPEN bit 2 of the SYSCON register

and the bit 3 of the new XPERCON register. Accesses to the XPORT9, XTIMER, XPORT10

and XADCMUX modules use a 16-bit demultiplexed bus mode without waitstate or

read/write delay (50ns access at 40MHz CPU clock). Byte and word access is allowed.

4.1

Visibility of XBUS peripherals

The XBUS peripherals can be separately selected for being visible to the user by means of

corresponding selection bits in the XPERCON register. If not selected (not activated with

XPERCON bit) before the global enabling with XPEN-bit in SYSCON register, the

corresponding address space, port pins and interrupts are not occupied by the peripheral,

thus the peripheral is not visible and not available. SYSCON register is described in

Section 19.2: System configuration registers.

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