ST10F280_12 datasheet(83/239 Pages) STMICROELECTRONICS

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ST10F280

PWM module

Doc ID 8673 Rev. 3

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11.2.1

Operating modes

The XPWM module provides four different operating modes:

●

Mode 0 Standard PWM generation (edge aligned PWM) available on all four channels

●

Mode 1 Symmetrical PWM generation (center aligned PWM) available on all four

channels

●

Burst mode combines channels 0 and 1

●

Single shot mode available on channels 2 and 3

Note:

The output signals of the XPWM module are XORed with the outputs of the respective bits

of XPOLAR register. After reset these bits are cleared, so the PWM signals are directly

driven to the output pins. By setting the respective bits of XPOLAR register to ‘1’ the PWM

signal may be inverted (XORed with ‘1’) before being driven to the output pin. The

descriptions below refer to the standard case after reset, i.e. direct driving.

Mode 0: standard PWM generation (edge aligned PWM)

Mode 0 is selected by clearing the respective bit XPMx in register XPWMCON1 to ‘0’. In this

mode the timer XPTx of the respective XPWM channel is always counting up until it reaches

the value in the associated period shadow register. Upon the next count pulse the timer is

reset to 0000h and continues counting up with subsequent count pulses. The XPWM output

signal is switched to high level when the timer contents are equal to or greater than the

contents of the pulse width shadow register. The signal is switched back to low level when

the respective timer is reset to 0000h, i.e. below the pulse width shadow register. The period

of the resulting PWM signal is determined by the value of the respective XPPx shadow

PWM_PeriodMode0 = [XPPx] + 1

The duty cycle of the XPWM output signal is controlled by the value in the respective pulse

width shadow register. This mechanism allows the selection of duty cycles from 0% to 100%

including the boundaries. For a value of 0000h the output will remain at a high level,

representing a duty cycle of 100%. For a value higher than the value in the period register

the output will remain at a low level, which corresponds to a duty cycle of 0%.

The Figure 20 illustrates the operation and output waveforms of a XPWM channel in mode 0

for different values in the pulse width register.

This mode is referred to as Edge Aligned PWM, because the value in the pulse width

(shadow) register only effects the positive edge of the output signal. The negative edge is

always fixed and related to the clearing of the timer.

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