ST10F280_12 datasheet(54/239 Pages) STMICROELECTRONICS

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Central Processing Unit (CPU)

ST10F280

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Doc ID 8673 Rev. 3

6.1

Multiplier-accumulator Unit (MAC)

The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order

to improve the performances of the ST10 Family in signal processing algorithms.

Signal processing needs at least three specialized units operating in parallel to achieve

maximum performance:

●

A Multiply-Accumulate Unit,

●

An Address Generation Unit, able to feed the MAC Unit with 2 operands per cycle,

●

A Repeat Unit, to execute series of multiply-accumulate instructions.

The existing ST10 CPU has been modified to include new addressing capabilities which

enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.

This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a

repeat unit.

The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-

accumulate, 32-bit signed arithmetic operations.

A new transfer instruction CoMOV has also been added to take benefit of the new

addressing capabilities.

6.1.1

Features

Enhanced addressing capabilities

●

New addressing modes including a double indirect addressing mode with pointer post-

modification.

●

Parallel Data Move: this mechanism allows one operand move during Multiply-

Accumulate instructions without penalty.

●

New transfer instructions CoSTORE (for fast access to the MAC SFRs) and CoMOV

(for fast memory to memory table transfer).

Multiply-accumulate unit

●

One-cycle execution for all MAC operations.

●

16 x 16 signed/unsigned parallel multiplier.

●

40-bit signed arithmetic unit with automatic saturation mode.

●

40-bit accumulator.

●

8-bit left/right shifter.

●

Full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic and

compare instructions.

Program control

●

Repeat Unit: allows some MAC co-processor instructions to be repeated up to 8192

times. Repeated instructions may be interrupted.

●

MAC interrupt (Class B Trap) on MAC condition flags.

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