STA381BWS datasheet(28/171 Pages) STMICROELECTRONICS

tên linh kiện	STA381BWS

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Device overview

STA381BWS

28/171

Doc ID 018937 Rev 6

4.2

Input oversampling

Figure 4 shows the input oversampling block in front of the main processing. When 32 kHz

Fs is used, the default x2 oversampling ratio can be increased to a x3.

Activating this feature, it is possible to have a 384 kHz PWM switching frequency (instead of

the default 256 kHz) when 32 kHz Fs is used.

When bit 0 of register PLLCFG1 is set to one, the feature is activated so that the PLL ratio is

modified to generate 49.152 MHz internal clock and the audio data path (after the input

oversampling block) is running at 96 kHz.

It is not recommended to use the x3 oversampling feature when Fs > 32 kHz because of the

PLL maximum frequency constraint.

4.3

STCompressorTM

The STCompressorTM (STC from now on) is a stereo, dual-band Dynamic Range Control

(DRC) and its main purpose is to provide optimum output power level control for speaker

protection, preserving as much as possible the original audio quality of the signal.

Two main I2C registers control the STC behavior: STCCFG0 and STCCFG1. On top of the

data flow control bits, these registers also allow enabling the checksum engine to protect the

STC filters from erroneous coefficients downloads, thus improving the final application

circuitry and safety of the speakers.

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