EDJ8232B5MB datasheet(1/142 Pages) ELPIDA

tên linh kiện	EDJ8232B5MB

Giải thích chi tiết về linh kiện	8G bits DDR3 SDRAM, DDP

PDF	142 Pages

Scroll/Zoom	100%

nhà sản xuất	ELPIDA [Elpida Memory]

Trang chủ	http://www.elpida.com/en

Logo

1 / 142 page

Document No. E1825E30 (Ver. 3.0)

Date Published March 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011-2012

DATA SHEET

8G bits DDR3 SDRAM, DDP

EDJ8232B5MB (256M words

 32 bits)

Specifications

 Density: 8G bits

 Organization

 32M words  32 bits  8 banks

 Package

 136-ball FBGA

 DDP: 2 pieces of 4G bits chip sealed in one

package

 Lead-free (RoHS compliant) and Halogen-free

 Power supply: VDD, VDDQ  1.5V  0.075V

 Data rate

 1600Mbps/1333Mbps (max.)

 4KB page size

 Row address: A0 to A14

 Column address: A0 to A9

 Eight internal banks for concurrent operation

 Interface: SSTL_15

 Burst lengths (BL): 8 and 4 with Burst Chop (BC)

 Burst type (BT):

 Sequential (8, 4 with BC)

 Interleave (8, 4 with BC)

 /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

 /CAS Write Latency (CWL): 5, 6, 7, 8

 Precharge: auto precharge option for each burst

access

 Driver strength: RZQ/7, RZQ/6 (RZQ = 240)

 Refresh: auto-refresh, self-refresh

 Refresh cycles

 Average refresh period

7.8

s at 0C  TC  85C

3.9

s at 85C  TC  95C

 Operating case temperature range

 TC = 0C to +95C

Features

 Double-data-rate architecture: two data transfers per

clock cycle

 The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

 Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

 DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

 Differential clock inputs (CK and /CK)

 DLL aligns DQ and DQS transitions with CK

transitions

 Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

 Data mask (DM) for write data

 Posted /CAS by programmable additive latency for

better command and data bus efficiency

 On-Die Termination (ODT) for better signal quality

 Synchronous ODT

 Dynamic ODT

 Asynchronous ODT

 Multi Purpose Register (MPR) for pre-defined pattern

read out

 ZQ calibration for DQ drive and ODT

 Programmable Partial Array Self-Refresh (PASR)

 /RESET pin for Power-up sequence and reset

function

 SRT range:

 Normal/extended

 Programmable Output driver impedance control

Số phần tương tự - EDJ8232B5MB

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Elpida Memory	EDJ8232E5MB	1Mb / 142P	8G bits DDR3L SDRAM, DDP
	EDJ8232E5MB-DJ-F	1Mb / 142P	8G bits DDR3L SDRAM, DDP
	EDJ8232E5MB-GN-F	1Mb / 142P	8G bits DDR3L SDRAM, DDP

More results

Mô tả tương tự - EDJ8232B5MB

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Elpida Memory	EDJ1104BDSE	1Mb / 147P	1G bits DDR3 SDRAM
	EDJ1104BASE	1Mb / 148P	1G bits DDR3 SDRAM
	EDJ1104BBSE	1Mb / 151P	1G bits DDR3 SDRAM
	EDJ1104BFBG	1Mb / 147P	1G bits DDR3 SDRAM
	EDJ1108BDBG	1Mb / 147P	1G bits DDR3 SDRAM
	EDJ5304BASE	1Mb / 130P	512M bits DDR3 SDRAM
	EDJ8216E5MB	1Mb / 142P	8G bits DDR3L SDRAM, DDP
	EDJ8232E5MB	1Mb / 142P	8G bits DDR3L SDRAM, DDP
Hynix Semiconductor	H5TQ4G43MMR	720Kb / 73P	4Gb DDR3 SDRAM DDP(2Gbx2)
Kingston Technology Far...	D1028AN9CPGRK-U	1Mb / 41P	8G bits DDR4 SDRAM

More results

EDJ8232B5MB bảng dữ liệu(PDF) 1 Page - Elpida Memory

EDJ8232B5MB bảng dữ liệu(HTML) 1 Page - Elpida Memory

Số phần tương tự - EDJ8232B5MB

Mô tả tương tự - EDJ8232B5MB

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL