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EDJ8232B5MB bảng dữ liệu(PDF) 49 Page - Elpida Memory

tên linh kiện EDJ8232B5MB
Giải thích chi tiết về linh kiện  8G bits DDR3 SDRAM, DDP
PDF  142 Pages
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nhà sản xuất  ELPIDA [Elpida Memory]
Trang chủ  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDJ8232B5MB bảng dữ liệu(HTML) 49 Page - Elpida Memory

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EDJ8232B5MB
Data Sheet E1825E30 (Ver. 3.0)
49
[DDR3-1333 Speed Bins]
Speed Bin
DDR3-1333H
CL-tRCD-tRP
9-9-9
Symbol
/CAS write
latency
min.
max.
Unit
Notes
tAA
13.125
20
ns
8
tRCD
13.125
ns
8
tRP
13.125
ns
8
tRC
49.125
ns
8
tRAS
36
9
 tREFI
ns
7
tCK (avg) @CL=5
CWL = 5
3.0
3.3
ns
1, 2, 3, 4, 5
CWL = 6, 7
Reserved
Reserved
ns
4
tCK (avg) @CL=6
CWL = 5
2.5
3.3
ns
1, 2, 3, 5
CWL = 6
Reserved
Reserved
ns
4
CWL = 7
Reserved
Reserved
ns
4
tCK (avg) @CL=7
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
< 2.5
ns
1, 2, 3, 4, 5
CWL = 7
Reserved
Reserved
ns
4
tCK (avg) @CL=8
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
< 2.5
ns
1, 2, 3, 5
CWL = 7
Reserved
Reserved
ns
4
tCK (avg) @CL=9
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
< 1.875
ns
1, 2, 3, 4
tCK (avg) @CL=10
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
< 1.875
ns
1, 2, 3
Supported CL
settings
5, 6, 7, 8, 9, 10
nCK
Supported CWL
settings
5, 6, 7
nCK
Notes: 1. The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When
making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are synchronized
by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the
next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating
CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next ‘Supported CL’.
3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg) (max.)
corresponding to CL selected.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table
DDR3-1333 Speed Bins which is not subject to production tests but verified by design/characterization.
6. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table
DDR3-1600 Speed Bins which is not subject to production tests but verified by design/characterization.
7. tREFI depends on operating case temperature (TC).
8. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min.) must be
13.125 ns or lower. SPD settings must be programmed to match.



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