EDJ8232B5MB datasheet(87/142 Pages) ELPIDA

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EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

Protocol Examples

Protocol Example: Read Out Predetermined Read-Calibration Pattern

Multiple reads from Multi Purpose Register, in order to do system level read timing calibration based on

predetermined and standardized pattern.

Protocol Steps:

 Precharge All

 Wait until tRP is satisfied

 MRS MR3, op-code “A2 = 1 “ and “A[1:0] = 00“

 Redirect all subsequent reads into the Multi Purpose Register, and load Pre-defined pattern into MPR.

 Wait until tMRD and tMOD are satisfied (Multi Purpose Register is then ready to be read). During the period

MR3 A2 =1, no data write operation is allowed.

 Read:

 A [1:0] = ‘00’ (Data burst order is fixed starting at nibble, always 00 here)

 A [2] = ‘0’ (For BL8, burst order is fixed as 0,1,2,3,4,5,6,7)

 A12(/BC) = 1 (use regular burst length of 8)

 All other address pins (including BA [2:0] and A10(AP)): don’t care.

 After RL = AL + CL, DRAM bursts out the predefined Read Calibration Pattern.

 Memory controller repeats these calibration reads until read data capture at memory controller is optimized.

 After end of last MPR read burst wait until tMPRR is satisfied.

 MRS MR3, op-code “A2 = 0“ and “A[1:0] = valid data but value are don’t care“

 All subsequent read and write accesses will be regular READs and WRITEs from/to the DRAM array.

 Wait until tMRD and tMOD are satisfied

 Continue with “regular” DRAM commands, like activate a memory bank for regular read or write access,

Valid

tMOD

tMRD

Notes: 1. READ with BL8 either by MRS or OTF

2. Memory Control must drive 0 on A[2:0]

VIH or VIL

Command

A[1:0]

A[2]

A[9:3]

A10(AP)

A[11]

A12(/BC)

A[15:13]

DQS, /DQS

tMPRR

PALL

MRS

NOP

READ

NOP

MRS

NOP

T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31

T39

tRP

tMOD

/CK

MPR Readout of Predefined Pattern, BL8 fixed Burst Order, Single Readout

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