EDJ8232B5MB datasheet(79/142 Pages) ELPIDA

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EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

Write Leveling (MR1)

For better signal integrity, DDR3 memory module adopts fly by topology for the commands, addresses, control

signals and clocks. The fly by topology has benefits for reducing number of stubs and their length but in other

aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes Controller hard to

maintain tDQSS, tDSS and tDSH specification. Therefore, the controller should support ’write leveling’ in DDR3

SDRAM to compensate the skew.

Write leveling is a scheme to adjust DQS to CK relationship by the controller, with a simple feedback provided by the

DRAM. The memory controller involved in the leveling must have adjustable delay setting on DQS to align the rising

edge of DQS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK, sampled with the rising

edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected.

The DQS delay established through this exercise would ensure tDQSS, tDSS and tDSH specification. A conceptual

timing of this scheme is shown as below.

diff_Clock

Source

Destination

Push DQS to

capture 0-1 transition

diff_DQS

diff_Clock

diff_DQS

Write Leveling Concept

DQS, /DQS driven by the controller during leveling mode must be terminated by the DRAM, based on the ranks

populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.

One or more data bits should carry the leveling feedback to the controller, each byte lane should be leveled

independently. Therefore, a separate feedback mechanism should be available for each byte lane.

DRAM Setting for Write Leveling and DRAM Termination Function in That Mode

DRAM enters into write leveling mode if A7 in MR1 set 1. And after finishing leveling, DRAM exits from write leveling

mode if A7 in MR1 set 0 (MR1 Setting Involved in the Leveling Procedure table).

Note that in write leveling mode, only DQS/DQS terminations are activated and deactivated via ODT pin, not like

normal operation (refer to the DRAM Termination Function in The Leveling Mode table)

[MR1 Setting Involved in the Leveling Procedure]

Function

MR1 bit

Enable

Disable

Note

Write leveling enable

Output buffer mode (Qoff)

A12

Note: 1. Output buffer mode definition is consistent with DDR2

[DRAM Termination Function in The Leveling Mode]

ODT pin@DRAM

DQS, /DQS termination

DQs termination

De-asserted

Off

Asserted

Off

Note: In write leveling mode with its output buffer disabled (MR1 [bit7] = 1 with MR1 [bit12] = 1) all RTT_Nom

settings are allowed; in write leveling mode with its output buffer enabled (MR1 [bit7] = 1 with MR1 [bit12] = 0)

only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.

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